Reference is now made to FIG. 1A showing a block diagram of an integrated circuit. The integrated circuit includes a core logic block configured to generate an output digital signal d. The core logic block is powered by a first power supply domain referenced to the supply voltages Vdd and Gnd. The digital signal d is received at the input of a level shifter circuit. The level shifter circuit converts the digital signal d from the first power supply domain to a second power supply domain and outputs a digital signal D. The second power supply domain is referenced to the supply voltages Vdde and Gnde. In an example, Vdde>Vdd and Gnde=Gnd. In such an example, Vdd=1.0V, Vdde=1.8V and Gnd=Gnde=0V. A predriver circuit receives the digital signal D and generates a p-MOS drive signal PD and an n-MOS drive signal ND from the signal D. The signals PD and ND have the same phase as the signal D but are slightly offset from signal D in the time domain. In an example, the predriver circuit may be implemented by buffer circuits in a manner known in the art. The predriver circuit is also powered from the second power supply domain. The signals PD and ND are applied to the inputs of a driver circuit 10 (the circuit details of which are shown in FIG. 1B, discussed below), with the driver circuit 10 generating an output signal applied to a pad (for example including a package pin) of the integrated circuit. The driver circuit 10 is also powered from the second power supply domain. The driver circuit is configurable with a variable drive strength selected by the core logic block through a configuration signal Si. The signal Si may, for example, be a multi-bit digital signal that is decoded by the driver circuit 10 to select the drive strength. A load, schematically illustrated here as a variable capacitance, is attached to the integrated circuit pad (pin) and is driven by the output signal.
Reference is now made to FIG. 1B showing a circuit diagram for the driver circuit 10.
The circuit 10 includes a plurality of half-bridge drive circuits 12 coupled in parallel. Each half-bridge drive circuit 12 comprises a p-channel MOSFET transistor 14 and an n-channel MOSFET transistor 16. The transistors 14 and 16 are formed as low threshold voltage (LVT) devices for high speed operation. The source-drain paths of the transistors 14 and 16 are coupled in series at an output node 18 (which is directly connected to the output pad). The source terminals of the transistors 14 are coupled to a first power supply node 20 of the second power supply domain. The source terminals of the transistors 16 are coupled to a second power supply node 22 of the second power supply domain. The power supply node 20 may, for example, be a positive power supply node (at supply voltage Vdde) and the power supply node 22 may, for example, be a ground power supply node (at supply voltage Gnde). The drain terminals of transistors 14 and 16 are coupled together at output node 18.
The driver circuit 10 is driven by the p-MOS drive signal PD and the n-MOS drive signal ND, where those signals are derived from the data signal D after buffering. The p-MOS drive signal PD is coupled to input line 24. The n-MOS drive signal ND is coupled to a second input line 26. The first input line 24 is coupled to the gate terminal of the transistor 14 in each half-bridge drive circuit 12. The second input line 26 is coupled to the gate terminal of the transistor 16 in each half-bridge drive circuit 12. Each of the transistors 14 and 16 includes, as known in the art, a body (or bulk) terminal. The body terminals of the transistors 14 and 16 are biased by the voltages at the first and second power supply nodes 20 and 22, respectively, for example by connecting the body terminal to the source terminal of each transistor.
The coupling of the gate terminals of the transistors in a first of the half-bridge drive circuits 12 to the lines 24 and 26, respectively, is a direct connection in an example implementation. The coupling of the gate terminals of the transistors in the other half-bridge drive circuits 12 to the lines 24 and 26, respectively, is an indirect connection made through a pass-gate circuit 26 (for example, formed of a single MOS transistor or a pair of parallel connected CMOS transistors). The pass gate circuits 26 are selectively actuated in response to the configuration signal Si to implement variable strength drive. A decoder circuit 28 receives and decodes the configuration signal Si to generate pass signals Pj for application to control selective actuation of each of the other half-bridge drive circuits 12 by selectively turning on the pass-gate circuit 26.